1. Field of the Invention
This invention relates to the field of current sources, and particularly to current source circuits and methods used to charge capacitive nodes.
2. Description of the Related Art
There is some amount of capacitance associated with every node in an electronic circuit. The capacitance may take the form of, for example, a discrete circuit element, a capacitive load, or a parasitic capacitance. Regardless of its form, a circuit node's capacitance affects the speed with which a signal connected to it can transition from one state to another, because the node's capacitance must be charged (if the node's voltage is to increase) or discharged (if the voltage is decreasing) before the transition can occur. This capacitance-induced time lag may be unacceptably long, adversely affecting the performance of circuitry which is ideally fast-responding.
Various techniques are employed to charge and/or discharge node capacitance. An example is illustrated in FIG. 1. A transmitter device 10 sends a signal 12 to a receiver device 14. A transmitter and a receiver often operate with different supply voltages. In such cases, a signal sent from transmitter to receiver is typically generated with an open drain or open collector transistor such as open-drain NMOS FET 16, and then referenced to the receiver's supply voltage with a pull-up device 18 in the receiver.
As noted above, a capacitance is associated with every circuit node. In FIG. 1, a parasitic capacitance C.sub.par is found at the junction of FET 16 and pull-up device 18. Transistor 16 can pull down signal 12 very rapidly, but when transistor 16 is off (indicating a "high" output), pull-up device 18 pulls up signal 12. However, before signal 12 can rise, C.sub.par must be charged, and the time required to do this slows a low-to-high transition of signal 12. For example, assume signal 12 is to transition from 0 to 3 volts (.DELTA.V=3 volts), pull-up device 18 provides 120 .mu.A (i.sub.pullup), and C.sub.par is 10 pf. The transition time .DELTA.t is given by: EQU .DELTA.t=C.sub.par *(.DELTA.V/i.sub.pullup)=250 ns
Once received by receiver 14, signal 12 is typically fed to a circuit 19 which detects a transition of signal 12. However, if transition time .DELTA.t is too long, the response speed of detection circuit 19 can be slowed such that it cannot meet its performance requirements.
Pull-up device 18 is conventionally a resistor or a fixed current source. A resistive pull-up can result in a low-to-high transition that is unacceptably slow, because the current charging C.sub.par will decrease as the signal 12 voltage increases. A fixed current source avoids this problem, but also has a major drawback in low power applications: in circuits where low power consumption is important, idle current--i.e., the current consumed when the circuit's inputs are not changing--is preferably low. A fixed current source, however, wastes power by continuously providing current as signal 12 transitions from high to low, and while signal 12 is in its low state.
Another common capacitive node situation is shown in FIG. 2. An operational amplifier 20 is driving a capacitive load C.sub.load at a node 22. A typical op amp includes an input stage 24 and an output stage 26. The input and output stages are biased from a fixed current source 28. If op amp 20 is suddenly required to increase its output voltage, the capacitance at node 22 must be charged, typically at a specified speed. The current to charge C.sub.load comes from the output stage. However, the ability of the output stage to drive a load is limited by the fixed amount of bias current available from current source 28 to drive the output stage transistors. While a large current source 28 would reduce the transition time, the size of the current source is often limited to minimize the consumption of supply current. Limiting the bias current, however, also acts to limit the speed with which node 22 can be charged or discharged and the output voltage changed.